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[AK1545] AK1545 3.5ghz low noise integer-n frequency synthesizer 1. overview the AK1545 is an integer-n pll (phase locked loop) freq uency synthesizer, covering a wide range of frequency from 500mhz to 3.5ghz. consisting of a highly accurate charge pump, a reference divider, a programmable divider and a dual-modulus prescaler (p/p+1), this product provides high performance, very low phase noise. an ideal pll can be achieved by combining the AK1545 with the external loop filter and vco (voltage controlled oscillator). access to the registers is c ontrolled via a 3-wire serial interface. the operating supply voltage is from 2.7v to 5.5v, and the charge pump circuit and the serial interface can be driven by individual supply voltage. 2. features ? operating frequency : 500mhz to 3.5ghz ? programmable charge pump current : 250 a and 1ma ? fast lock mode : the charge pump cu rrent is switched by this function. ? supply voltage : 2.7 to 5.5 v (avdd, dvdd pins) ? separate charge pump power supply : avdd to 5.6v (cpvdd pin) ? excellent phase noise : -217dbc/hz ? on-chip lock detection feature of pll : selectab le phase frequency detector (pfd) output or digital filtered lock detect ? package : 16pin tssop ? operating temperature : -40c to 85c ms1471-e-00 1 2012/10
[AK1545] - table of contents - 1. overview ____________________________________________________________________________ 1 2. features ____________________________________________________________________________ 1 3. block diagram _______________________________________________________________________ 3 4. pin functional description and assignments _____________________________________________ 4 5. absolute maximum ratings ____________________________________________________________ 6 6. recommended operating range ________________________________________________________ 6 7. electrical characteristics ______________________________________________________________ 7 8. block functional descriptions _________________________________________________________ 11 9. register map _______________________________________________________________________ 19 10. function description - registers _______________________________________________________ 21 11. ic interface schematic _______________________________________________________________ 29 12. recommended connection schematic of off-chip component _____________________________ 31 13. power-up timing chart (recommended flow) ____________________________________________ 33 14. frequency setting timing chart (recommended flow) ____________________________________ 34 15. typical evaluation board schematic ____________________________________________________ 35 16. typical performance characteristics ____________________________________________________ 36 17. outer dimensions ___________________________________________________________________ 37 18. marking ____________________________________________________________________________ 38 in this specification, the following notations ar e used for specific signal and register names. [name] : pin name : register group name (address name) {name} : register bit name ms1471-e-00 2 2012/10
[AK1545] 3. block diagram cp phase freqency detector refin + - prescaler 32/33 programable counter 13 bit lock detect rfinp rfinn cpvdd vss a vdd ld clk data le register 21 bit n divider fast counter pdn test2 test1 r counter 14 bit sw charge pump swallow counter 5 bit dvdd fig. 1 block diagram ms1471-e-00 3 2012/10
[AK1545] 4. pin functional description and assignments table 1 pin functions no. name i/o pin functions power down (note 1) remarks 1 sw do fast lock switch output 2 cp ao charge pump output ?hi-z? 3 vss g ground 4 test1 di test input 1. this pin must be connected to ground. schmidt trigger input 5 rfinn ai complementary input to the rf prescaler 6 rfinp ai input to the rf prescaler 7 avdd p power supply for analog blocks 8 refin ai reference signal input 9 test2 di test input 2. this pin must be connected to ground. schmidt trigger input 10 pdn di power down schmidt trigger input 11 clk di serial clock input schmidt trigger input 12 data di serial data input schmidt trigger input 13 le di load enable input schmidt trigger input 14 ld do lock detect output 15 dvdd p power supply for digital blocks 16 cpvdd p power supply for charge pump note 1) ?power down? means the state of [pdn] =?low? after power on. the following table shows the meaning of ab breviations used in the ?i/o? column. ai: analog input pin ao: analog output pin aio: analog i/o pin di: digital input pin do: digital output pin p: power supply pin g: ground pin ms1471-e-00 4 2012/10
[AK1545] 2. pin assignments 1 2 3 4 5 6 7 8 9 10 15 14 13 12 11 16 top view sw cp vss rfinn test1 data le ld dvdd cpvdd rfinp avdd refin clk pdn test2 16pin tssop fig. 2 pin assignment ms1471-e-00 5 2012/10
[AK1545] 5. absolute maximum ratings table 2 absolute maximum ratings parameter symbol min. max. unit remarks vdd1 -0.3 6.5 v [avdd], [dvdd] (note 1) supply voltage vdd2 -0.3 6.5 v [cpvdd] (note 1) ground level vss 0 0 v [vss] analog input voltage vain vss-0.3 vdd1+0.3 v [rfinn], [rfinp], [refin] (notes 1 & 2) digital input voltage vdin vss-0.3 vdd1+0.3 v [clk], [data], [le], [pdn] (notes 1 & 2) input current iin -10 10 ma storage temperature tstg -55 125 c note 1) 0v reference for all voltages. note 2) maximum must not be over 6.5v. exceeding these maximum ratings may result in damage to the AK1545. normal operation is not guaranteed at these extremes. 6. recommended operating range table 3 recommended operating range parameter symbol min. typ. max. unit remarks operating temperature ta -40 85 c vdd1 2.7 5.5 v applied to the [avdd],[dvdd] pins supply voltage vdd2 vdd1 5.6 v applied to the [cpvdd] pin note 1) vdd1 and vdd2 can be driven individually within the recommended operating range. note 2) all specifications are applicable within the recommended operating range (operating temperature / supply voltage). ms1471-e-00 6 2012/10
[AK1545] 7. electrical characteristics 1. digital dc characteristics table 4 digital dc characteristics parameter symbol conditions min. typ. max. unit remarks high level input voltage vih 0.8 vdd1 v note 1) low level input voltage vil 0.2 vdd1 v note 1) high level input current iih vih = vdd1=5.5v -1 1 a note 1) low level input current iil vil = 0v, vdd1=5.5v -1 1 a note 1) high level output voltage voh ioh = -500 a vdd1-0.4 v note 2) low level output voltage vol iol = 500 a 0.4 v note 3) high level output voltage2 voh ioh = -500 a vdd2-0.4 v note 4) note 1) applied to the [ clk ], [ data ], [ le ] and [ pdn ] pins. note 2) applied to the [ ld ] pins. note 3) applied to the [ld],[sw] pins. note 4) applied to the [ sw] pins. ms1471-e-00 7 2012/10
[AK1545] 2. serial interface timing le (input) clk (input) data (input) ts u thd tcsu d18 d2 a0 a1 d0 d1 tc h tc l tlesu tle fig. 3 serial interface timing chart table 5 serial interface timing parameter symbol min. typ. max. unit remarks clock l level hold time tcl 25 ns clock h level hold time tch 25 ns clock setup time tcsu 10 ns data setup time tsu 10 ns data hold time thd 10 ns le setup time tlesu 10 ns le pulse width tle 20 ns ms1471-e-00 8 2012/10
[AK1545] 3. analog circuit characteristics vdd1 2.7v to 5.5v, vdd2=vdd1 to 5.6v, ?40c ta 85c, unless otherwise specified. parameter min. typ. max. unit remarks rf characteristics input sensitivit y -10 2 dbm input frequency 500 3500 mhz refin characteristics input sensitivity 0.4 vdd1 vpp input frequency 5 100 mhz maximum allowable prescaler output frequency 120 mhz phase detector phase detector frequency 55 mhz charge pump charge pump high value 1 ma charge pump low value 250 a icp tri-state leak current 1 na 0.6 vcpo vdd2-0.7, ta=25c mismatch between source and sink currents (note 1) 3 % vcpo=vdd2/2, ta=25c icp vs. vcpo (note 2) 2 % 0.5 vcpo vdd2-0.5, ta=25c noise characteristic normalized phase noise floor -217 dbc/hz current consumption idd1 10 a [pdn]=?0? or {pd1}=1 idd2 (note3, note4) 12 18 ma [pdn]=?1?, {pd1}=0, idd for vdd1 idd3 (note4) 0.4 0.7 ma [pdn]=?1?, {pd1}=0, idd for vdd2 note 1) mismatch between source and sink currents : [(|isink|-|isource|)/{(|isink|+|isource|)/2}] 100 [%] note 2) see ?charge pump characteristics - voltage vs. current?. vcpo is the output voltage at [cp]. icp vs. vcpo : [{1/2(|i1|-|i2|)}/{1/2(|i1|+|i2|)}]100 [%] note 3) when [pdn] = ?1? and {pd1}=0, the total powe r supply current of the AK1545 is ?idd2+idd3+ charge pump current?. note 4) rfin=3.5ghz,5dbm, refin= 100mhz,10dbm, {r}=100,{b}=109,{a}=12 ms1471-e-00 9 2012/10
[AK1545] isink isource vcpo icp cpvdd-0.5 cpvdd/2 0.5 i1 i1 i2 i2 fig. 4 charge pump characteristics - vo ltage (vcpo) vs. current (icp) ms1471-e-00 10 2012/10
[AK1545] 8. block functional descriptions 1. frequency setup the following formula is used to calculate the frequency setting for the AK1545. frequency setting (external vco output frequency) = f pfd x n where : n : dividing number n = [ (p x b) + a ] f pfd : phase detector frequency f pfd = [refin] pin input frequency / r counter dividing number p : 32 b : b (programmable) counter value (see :{b[12:0]}) a : a (swallow) counter value (see :{a[4:0]}) calculation example the output frequency of external refe rence frequency oscillator is 10mhz, and f pfd is 1mhz and vco frequency is 3000mhz. AK1545 setting : r (reference counter) =10000000/100000 0 = 10 (:{r[13:0]}= ?10?) p=32 b=93 (:{b[12:0]}=?93?) a=24 (:{a[4:0]}=?24?) frequency setting = 1m [ (3293) + 24] = 3000mhz lower limit for setting consecutive dividing numbers in the AK1545, it is not possible to set cons ecutive dividing numbers below the lower limit. (the lower limit is determined by a dividing number set for the prescaler.) the following table shows an example where consecutive di viding numbers below the lower limit cannot be set. the consecutive dividing numbers can be set when b p-1. ms1471-e-00 11 2012/10
[AK1545] p=32 (dual modulus prescaler 32/33) p b[12:0] a[5:0] n [ (pb) + a ] remarks 32 30 30 990 991 cannot be set as an n divider. 32 31 0 992 this is the lower limit. 992 or over can consecutively be set as an n divider. 32 31 1 993 ? ? ? ? 32 4097 15 131119 ? ? ? ? 32 8191 30 262142 32 8191 31 262143 ms1471-e-00 12 2012/10
[AK1545] 2 charge pump, loop filter and fast lock up mode the current setting of charge pump and loop filter can switch with the built-in timer for fast lock. c2 phase detector up down timer vco loop filter c1 c3 r2 r3 cp sw r2? fig. 5 loop filter schematic fast lock mode 1 the output level of [sw] pin is programmed to a low state, and the charge pump current is switched to the high value (1 ma). [sw] is used to switch a resistor in the loop filter and to ensure stability while in the fast lock up mode by altering the loop bandwidth. when the {cpgain} bit in the n register is set to ?1?, the AK1545 enters the fast lock up mode. when the {cpgain} bit in the n register is set to ?0?, the AK1545 exits the fast lock up mode. fast lock mode 2 the output level of [sw] pin is programmed to a low state, and the charge pump current is switched to the high value (1 ma). [sw] is used to switch a resistor in the loop filter and to ensure stability while in the fast lock up mode by altering the loop bandwidth. when the {cpgain} bit in the n register is set to ?1?, the AK1545 enters the fast lock up mode. the AK1545 exits the fast lock up mode after the expiration of the timer. the timer configuration is set by the value in {timer [3:0]}. after the timeout, the {cpgain} bit in the n register is automatically reset to 0, and the device reverts to normal mode instead of the fast lock up mode. ms1471-e-00 13 2012/10
[AK1545] fast lock up high value vss normal normal low value hi-z low value hi-z operation mode charge pump current [sw] pin control fast lock up time s p ecified b y the timer fig. 6 fast lock up mode timing chart table 6 fast lock mode function function {fasten}={d7} {fastmode}={d9} {cpgain} [sw]-pin state 0 fast lock mode disable 0 x 1 {d9} state 0 hi-z fast lock mode 1 1 0 1 vss fast lock mode 2 1 1 (*1) controlled by the value in {timer [3:0]}. (*1) when the timer is counting, {cpgain} =?1? and [sw] pi n is low state. after the timeout, its function reverts to normal mode ({cpgain} =?0? and [sw] pin is hi- z state) instead of the fast lock up mode. [sw]-pin functions sw pin is a general purpose output (gpo) pi n which can be controlled by fasten register. (1) {fasten} =?0? the value of d9 register comes out from the sw pin. AK1545 sw fastmode [d9] 0 ? : ? sw ?low? ? (cpvss) fastmode [d9] 1 ? : ? sw ?high? ? (cpvdd) (2) {fasten} =?1? works as shown in the ?fast lock up mode timing chart? above. ms1471-e-00 14 2012/10
[AK1545] 3 lock detect lock detect output can be selected by {ld[2:0]} in . when {ld} is set to ?101bin", the phase detector outputs an un-manipulated phase detection(comparison) resul t. (this is called ?analog lock detect?.) when {ld} is set to ?001bin?, the lock detect signal is output according to the on-chip logic. (this is called ?digital lock detect?.) the lock detect can be done as following: the [ld] pin is in unlocked state (which outputs ?low?) wh en a frequency setup (n register or r register settings) is made. case of lock to unlock is as following. r=1: the [ld] pin outputs ?high? when a phase error smal ler than a half cycle of [refin] (1/2t) is detected for the counter value n times consecutively. r>1: the [ld] pin outputs ?high? when a phase error sm aller than a cycle of [refin] (t) is detected for the counter value n times consecutively. case of unlock to lock is as following. r=1: the [ld] pin outputs ?low? when a phase error larger than a half cycle of [refin] (1/2t) is detected for the counter value n times consecutively. r>1: the [ld] pin outputs ?low? when a phase error larger than a cycle of [refin] (t) is detected for the counter value n times consecutively. the counter value n can be set by {ldp} in . the n is different between ?unlocked to locked? and ?locked to unlocked?. table 7 lock detect precision {ldp} unlocked to locked locked to unlocked 0 n=15 n=3 1 n=31 n=7 ms1471-e-00 15 2012/10
[AK1545] the lock detect signal is shown below: reference clock 1/2t this is ignored because it cannot be sampled. pfd frequency signal divided clock of rf input signal pfd output signal (phase error) i g nored valid ld output the [ld] pin outputs high when a phase error smaller than 1/2t is detected for n times consecutively. valid case of ?r = 1? reference clock t this is ignored because it cannot be sampled. valid pfd frequency signal divided clock of rf input signal pfd output signal (phase error) ignored ignored the [ld] pin outputs high when a phase error smaller than t is detected for n times consecutively. valid ld output case of ?r > 1? fig. 7 digital lock detect operations ms1471-e-00 16 2012/10
[AK1545] phase error < t flag = flag+1 lock ([ld]=high) unlock ([ld]=low) y es no flag > n flag=0 y es no fig. 8 unlocked locked phase error > t y es flag=0 flag = flag+1 flag > n no y es unlock ([ld]=low) no lock ([ld]=high) pdn=0 or {pd1}=1 fig. 9 locked unlocked ms1471-e-00 17 2012/10
[AK1545] 4 reference counter the reference input can be set with a dividing number in t he range of 1 to 16383 using {r [13:0]}, which is an 14-bit address of {d[13:0]} in . 0 cannot be set as a dividing number. 5 prescaler the dual modulus prescaler (p/p + 1) and the swallow counter are used to provide a large dividing ratio. AK1545 has a dual modulus prescaler 32/33. 6 power-down and power-save mode it is possible to operate in the power-down or power-save mode if necessary by using the external control pin. power on follow the power-up sequence. normal operation table 8 power-down and power-save mode [pdn] {pd2} {pd1} function ?low? x x power down ?high? x 0 normal operation ?high? 0 1 asynchronous power down ?high? 1 1 synchronous power down x : don?t care ms1471-e-00 18 2012/10
[AK1545] 9. register map name data address r counter 0 0 n counter (a and b) 0 1 function 1 0 initialization d18 - d0 1 1 name d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 addr ess r count ldp 0 0 0 0 r [13] r [12] r [11] r [10] r [9] r [8] r [7] r [6] r [5] r [4] r [3] r [2] r [1] r [0] 0x0 n count cpga in b [12] b [11] b [10] b [9] b [8] b [7] b [6] b [5] b [4] b [3] b [2] b [1] b [0] a [4] a [3] a [2] a [1] a [0] 0x1 func. 0 pd2 0 0 0 timer [3] timer [2] timer [1] timer [0] fast mode 0 fast en cp hiz cp pola ld [2] ld [1] ld [0] pd1 cntr rst 0x2 initial. 0 pd2 0 0 0 timer [3] timer [2] timer [1] timer [0] fast mode 0 fast en cp hiz cp pola ld [2] ld [1] ld [0] pd1 cntr rst 0x3 ms1471-e-00 19 2012/10
[AK1545] notes for writing into registers after powers on AK1545, [pdn] mu st be ?0? or {pd1} must be ?1?. after powers on AK1545, the initial registers value are not defined. it is required to write the data in all addresses in order to commit it. [examples of writing into registers] (ex. 1) power-on - bring [pdn] to ?0 (low)? - apply vdd - program address0, address1 and address2 - bring [pdn] to ?1 (high)? (ex. 2) changing frequency settings : initialization - program address3 - program address1 (ex. 3) changing frequency settings : counter reset - program address2. as part of this, load ?1? to both {pd1} and {cntr_rst}. - program address1 - program address2. as part of this, load ?0? to both {pd1} and {cntr_rst}. (ex. 4) changing frequency settings : pdn pin method - bring [pdn] to ?0 (low)? - program address1 - bring [pdn] to ?1 (high)? ms1471-e-00 20 2012/10
[AK1545] 10. function description - registers < address0 : r counter > d18 d[17:14] d[13:0] address ldp 0 r[13:0] 00 d[17:14] : these bits are set to the following for normal operation d17 d16 d15 d14 0 0 0 0 ldp : lock detect precision the counter value for digital lock detect can be set. d18 function remarks 15 times count unlocked to locked 0 3 times count locked to unlocked 31 times count unlocked to locked 1 7 times count locked to unlocked ms1471-e-00 21 2012/10
[AK1545] r[13:0] : reference clock division number the following settings can be selected for the reference clock division. the allowed range is 1 (1/1 division) to 16383 (1/16383 division). 0 cannot be set. the maximum frequency for f pfd is 55mhz. d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 prohibited 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1/1 division 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1/2 division 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1/3 division 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1/4 division data 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1/16381 division 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1/16382 division 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1/16383 division ms1471-e-00 22 2012/10
[AK1545] < address1 : n counter > d18 d[17:5] d[4:0] address cpgain b[12:0] a[4:0] 01 cpgain : sets the charge pump current d18 function remarks 0 250 a 1 1ma b[12:0] : b (programmable) counter value d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 function remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 prohibited 0 0 0 0 0 0 0 0 0 0 0 0 1 1 dec prohibited 0 0 0 0 0 0 0 0 0 0 0 1 0 2 dec prohibited 0 0 0 0 0 0 0 0 0 0 0 1 1 3 dec data 1 1 1 1 1 1 1 1 1 1 1 0 1 8189 dec 1 1 1 1 1 1 1 1 1 1 1 1 0 8190 dec 1 1 1 1 1 1 1 1 1 1 1 1 1 8191 dec a[4:0] : a (swallow) counter value d4 d3 d2 d1 d0 function remarks 0 0 0 0 0 0 0 0 0 0 1 1 dec 0 0 0 1 0 2 dec 0 0 0 1 1 3 dec data 1 1 1 0 1 29 dec 1 1 1 1 0 30 dec 1 1 1 1 1 31 dec ms1471-e-00 23 2012/10
[AK1545] * requirements for a[4:0] and b[12:0] the data at a[4:0] and b[ 12:0] must meet the following requirements: a[4:0] 0, b[12:0] 3, b[12:0] a[4:0] see ?frequency setup? in section ?block functional descriptions? for details of the relationship between a frequency division number n and the data at a[ 4:0] and b[12:0]. ms1471-e-00 24 2012/10
[AK1545] < address2 : function > d18 d17 d[16:14] d[13:10] d9 d8 d7 0 pd2 0 timer[3:0] fastmode 0 fasten d6 d5 d[4:2] d1 d0 address cphiz cppola ld[2:0] pd1 cntr_rst 02 pd2, pd1 : power down select [pdn] {pd2} {pd1} function ?low? x x power down ?high? x 0 normal operation ?high? 0 1 asynchronous power down ?high? 1 1 synchronous power down x : don?t care {pd2}=1 and {pd1}=1 : all circuits powers down at the timing when the phase detector frequency signal reverses. {pd2}=0 and {pd1}=1 : all circuits goes into power down at the rise up of le signal that latches 1 into {pd1}. timer[3:0] : sets the fast lock timer this is enabled when { fastmode } =?1?, {fasten} = ?1? and {cpgain}=?1?. the charge pump current is set into high value (1ma) designate during switchover time which is set by {timer[3:0]}. the following formula shows the relationship betwe en the switchover time and the counter value. switchover time = 1 / f pfd x counter value counter value = 3 + timer[3:0] x 4 ms1471-e-00 25 2012/10
[AK1545] the following table shows the relationship between counter value and {timer[3:0]}. d13 d12 d11 d10 function remarks 0 0 0 0 3 counts 0 0 0 1 7 counts 0 0 1 0 11 counts 0 0 1 1 15 counts 0 1 0 0 19 counts 0 1 0 1 23 counts 0 1 1 0 27 counts 0 1 1 1 31 counts 1 0 0 0 35 counts 1 0 0 1 39 counts 1 0 1 0 43 counts 1 0 1 1 47 counts 1 1 0 0 51 counts 1 1 0 1 55 counts 1 1 1 0 59 counts 1 1 1 1 63 counts fastmode and fasten : enables or disables the fast lock mode d7 d9 function remarks 0 x fast lock mode disable sw pin functions as a general purpose output (gpo) which reflects a d9 register settings. 1 0 fast lock mode 1 1 1 fast lock mode 2 timer is available cphiz : tri-state output setting for charge pump d6 function remarks 0 charge pumps are activated. use this setting for normal operation. 1 tri-state note 1) note 1) the charge pump output is turned off and put in the high- impedance (hi-z) state. ms1471-e-00 26 2012/10
[AK1545] cppola : selects positive or negative output polarity for cp d5 function remarks 0 negative 1 positive high high charge pump output voltage negative positive low low vco frequency ld selects output from [ld] pin d4 d3 d2 function remarks 0 0 0 low 0 0 1 digital lock detect 0 1 0 n divider output 0 1 1 high 1 0 0 r divider output 1 0 1 analog lock detect open drain 1 1 0 low 1 1 1 low cntr_rst : counter reset d0 function remarks 0 normal operation 1 r and n counters are reset. ms1471-e-00 27 2012/10
[AK1545] < address3 : initialization > this function is same as . when this register is programm ed, the n-counter, r-counter, fast-counter become load-state conditi on and the charge pump output is th ree - state. next, writing the address1, these are starting to operation. ms1471-e-00 28 2012/10
[AK1545] 11. ic interface schematic no. pin name i/o r0( ) cur( a) function 10 pdn i 300 11 clk i 300 12 data i 300 13 le i 300 4 test1 i 300 9 test2 i 300 digital input pin r0 14 ld o 1 sw o digital output pin 8 refin i 300 analog input pin r0 ms1471-e-00 29 2012/10
[AK1545] no. pin name i/o r0( ) cur( a) function 2 cp o analog output pin 5 rfinn i 21k 60 6 rfinp i 21k 60 analog input pin (rf input pin) r0 ms1471-e-00 30 2012/10
[AK1545] 12. recommended connection sche matic of off-chip component 1. power supply pins pvdd cpvdd lsi a vdd 100pf 10 f 0.01 f 0.01 f 0.01 f 100pf 10 f 100pf 10 f 2. test1, test2 test1,2 lsi 3. refin refin lsi 100pf10% ms1471-e-00 31 2012/10
[AK1545] 4. rfinp rfinn lsi rfinp vco output rfinn 100pf10% 100pf10% 51? ms1471-e-00 32 2012/10
[AK1545] 13. power-up timing chart (recommended flow) note1) after vdd1 and vdd2 is powered up, the initial setting of registers is undefined. it is required to write in address0, 1 and 2. internal register values are set address 0~2 hi-z output vdd1, vdd2 pdn register write-in cp fig. 10 power up sequence (recommended) internal sequence ci rcuit is initialized internal register values are set output hi-z undefined address 2 {pd1}=0 address 0,1 {pd1}=1 address 2 vdd1, vdd2 pdn register write-in cp note2) when vdd1, vdd2 and pdn are synchronously powered up, internal sequence circuit is not initialized. so the circuit starts working on undef ined status. therefore, register {pd1} must be set to ?1? before register setting. ms1471-e-00 33 2012/10
[AK1545] fig. 11 power up sequence (vdd1/vdd2/pdn synchronous power-up) 14. frequency setting timing chart (recommended flow) hi-z address 2 output 1 address 0 setting address 1 setting {pd1}=0 address 2 power up power down {pd1}=1 output 2 vdd1, vdd2 pdn register write-in cp fig. 12 frequency settings (controlled by {pd1}) pdn vdd1, vdd2 cp output 2 hi-z address 3 address 0 setting setting address 1 {pd1}=0 register write-in output 1 fig. 23 frequency settings (controlled by initial register) ? ) the function of address3 is the same as addre ss2. before writing in address3, be sure to set ms1471-e-00 34 2012/10
[AK1545] {pd1}=0. access to address3 resets cp to hi-z, then set address0 and 1. access to address1 restarts cp to operating. 15. typical evaluation board schematic c2 AK1545 loop filter c1 c3 r2 r3 cp rfout 51 100pf rfinn vco rfinp 100pf refin 100pf 100pf 18 18 18 sw r2? fig. 34 typical evaluation board schematic ms1471-e-00 35 2012/10
[AK1545] 16. typical performance characteristics -1khz \ 100 \ 90 \ 80 \ 70 \ 60 \ 50 \ 40 \ 30 \ 20 \ 10 0 output ? power ?\ db vdd1 = 3v, vdd2 = 5v icp = 1ma pfd freqency = 1mhz loop bandwidth = 100khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 0.19 seconds averages = 26 reference level = -5.27dbm 2800mhz +1khz +2khz -2khz -1khz -86.6dbc/hz -1khz \ 110 \ 100 \ 90 \ 80 \ 70 \ 60 \ 50 \ 40 \ 30 \ 20 \ 10 0 output ? power ?\ db vdd1 = 3v, vdd2 = 5v icp = 1ma pfd freqency = 1mhz loop bandwidth = 100khz res. bandwidth = 3khz video bandwidth = 3khz sweep = 2.2 seconds averages = 4 reference level = -6.29dbm 2800mhz +1mhz +2mhz -2mhz -1mhz -84.3dbc fig. 15 AK1545 phase noise (2800 mhz, 1 mhz, 100 khz) fig. 17 AK1545reference spurs (2800 mhz, 1 mhz, 100 khz) vdd=3v(?) cpvdd=5v(5052b) icp=1ma ref in=100mhz pdf=25khz lf=3khz \ 140 \ 130 \ 120 \ 110 \ 100 \ 90 \ 80 \ 70 \ 60 \ 50 \ 40 phase ? noise ?\ dbc/hz 1mhz 100hz frequency offset from 2.8ghz carrier 1.25 rms rms noise = 1.253 10db/division r l = -40 dbc/hz fig. 16 AK1545 integrated phase noise (2800 mhz, 1 mhz, 100 khz) ms1471-e-00 36 2012/10
[AK1545] 17. outer dimensions fig. 18 outer dimensions ms1471-e-00 37 2012/10
[AK1545] 18. marking a. style tssop b. number of pins 16 c. a1 pin marking d. product number 1545 e. date code ywwle (5 digits) y lower 1 digit of calendar year (year 2012-> 2, 2013-> 3 ...) ww week l lot identification, given to each product lot which is made in a week (a, b, c?) lot id is given in alphabetical order e fixed 1545 ( d ) ywwle ( e ) ( c ) ms1471-e-00 38 2012/10
[AK1545] important notice z these products and their specifications are subject to change without notice. when you consider any use or applicati on of these products, please make i nquiries the sales office of asahi kasei microdevices corporation (akm) or authorized di stributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustra te the operation and application examples of the semiconductor products. you are fully responsible for the incorporat ion of these external circuits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or syst ems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express writt en consent by representative director of akm. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assu me any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. ms1471-e-00 39 2012/10

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